The present disclosure relates generally to fabrication of integrated circuits, semiconductor devices and other miniaturized devices, and more particularly, to the integration of through substrate vias (“TSVs”) in a complementary metal-oxide semiconductor (“CMOS”) device.
Currently, the configuration of semiconductor chips only allows for chips to be bonded side to side or using wire bonding. The available bonding methods for the semiconductor chips have been limited due to the placement of the various elements on the semiconductor chips. Generally, when chips are manufactured, the TSVs are created after the contacts and transistors have been applied to the chips. By inserting the TSVs after the contacts and transistors, the chip loses surface space and unreliable regions are created within the 3D stacks of chips. In addition, when the TSVs are inserted last, the contacts must be made of tungsten in order to reduce the likelihood of the contacts being damaged during the annealing process of the TSVs. When tungsten contacts are used, the speed of the semiconductor chips generally slows down due to the resistivity of the tungsten contacts increasing. The current configurations also limit where you can wire because if the TSVs are created last, wiring will have to be done around the TSVs.
The present disclosure contemplates a new and improved apparatus and method for integrating TSVs in CMOS devices that overcome the current limitations.